The microcontroller has an arithmetic unit (or simply, CPU) and resources performing a variety of functions, and executes internal operation in synchronization with externally supplied clock. The resources performing a variety of functions exemplarily include a communication macro communicating with outside, and a pulse generation circuit generating pulses or clock signals at calculated or designated timing. The CPU controls resources by executing a predetermined program stored in a built-in memory and supplying control data to these resources. Each resource performs operation such as communication control and pulse generation, based on the control data, etc.
FIG. 1 shows a typical configuration diagram of the conventional microcontroller. A microcontroller 1 is provided with an arithmetic unit, i.e. CPU, a memory 10 having a program storage area and a temporary recording area, and internal resources including a pulse generation circuit such as a timer 12, a communication macro 18, etc. These internal resources are interconnected through an internal bus 2. Timer 12 includes at least a bus interface 14 interfacing internal bus 2, and a counter 16 generating pulses. Timer 12 is supplied with control data, etc. from the CPU, and outputs pulse S16 to internal or external circuits at predetermined timing counted by counter 16. Communication macro 18 is exemplarily provided with at least a bus interface 20 interfacing internal bus 2, and a counter 22 generating communication clock S22, to control input/output data communication from/to the outside.
Microcontroller 1 is supplied with clock CLK externally. The CPU and bus interfaces 14, 20 operate in synchronization with the same clock CLK. Also, counters 16, 22 perform count operation in synchronization with this clock CLK. For the purpose of bus control, it is necessary for bus initiator and target units to operate with the same clock, and bus interfaces 14, 20 are so structured as to operate in synchronization with the clock.
Such a microcontroller is exemplarily disclosed in a patent document 1 described later. This patent document 1 also discloses a method for reducing battery power consumption by decreasing an internal clock speed when a battery power voltage becomes low, with the provision of a rate multiplier/prescaler, thereby enabling a clock frequency to be variable corresponding to the battery source voltage.
As described above, in the microcontroller shown in FIG. 1, the CPU and the internal resources operate in synchronization with the externally supplied clock CLK. Here, it is required to increase a frequency of the supplied clock CLK to increase CPU processing capacity. By simply multiplying the frequency of the supplied clock CLK by N times, the CPU processing capability can be increased by N times. However, because counters 16, 22 in the internal resources 12, 18 operate in synchronization with the same supplied clock CLK, when the frequency of the supplied clock CLK is increased, control timing of the internal resources 12, 18 also becomes faster. This may impede proper control of units to be controlled by each internal resource. To avoid this, it becomes necessary to vary values to be loaded into counters 16, 22, increase the number of bits constituting the counters, etc. However, when the supplied clock CLK becomes still faster, the counter configuration in the internal resource have to be modified each time. To modify the internal resource configuration means modification of the microcontroller design, which causes a cost increase.
FIG. 2 shows another configuration diagram of the conventional microcontroller. This microcontroller 1 is provided with a frequency divider 30 dividing the frequency of the clock CLK, by which a second clock CLK2 having a lower speed is generated. This low-speed second clock CLK2 is supplied to the internal resources 12, 18. With such a configuration, it becomes possible for the internal resources 12, 18 to operate synchronously with the clock CLK2 having the original speed, not the increased speed, even when the speed of the clock CLK is set higher in order to increase the CPU processing capability. Thus, control function with proper timing can be maintained.
In a patent document 2, as an example, a method of using the divided clock CLK as internal control clock is disclosed. In this patent document 2, there is disclosed a method of detecting a control clock speed generated by a CPU, and the clock, of which frequency is divided with a frequency division ratio corresponding to the detected speed, is supplied to an interruption control circuit, namely a resource. With such a configuration, an interruption control speed can be maintained constant, even when the CPU operation speed is increased by the increased clock speed.
[Patent document 1] The official gazette of the Japanese Unexamined Patent Publication No. 2002-202829 (published on 19th of Jul., 2002.)
[Patent document 2] The official gazette of the Japanese Unexamined Patent Publication No. Hei-8-249082. (published on 27th of Sep., 1996.)